UK · A-Levels

Signal conversion

Real-world signals are analogue but modern processing is digital, so conversion between the two domains is essential. This chapter explains why conversion is needed and develops the digital-to-analogue converter (the summing DAC), the resolution and quantisation of an analogue-to-digital converter, and the flash and successive-approximation ADC architectures.

4 sections~15 min reading time3 competencies

T·0777 / 16

Exam profile

AO1 · Explain the need for conversion and describe DAC and ADC operation and architectures.AO2 · Calculate resolution, step size, number of levels and DAC and ADC outputs and codes.AO3 · Evaluate resolution against speed and cost and choose a converter for a specification.

Operators:explaindescribecalculatedeterminedesignanalyseevaluate

basic level

At AS the focus is the reason for conversion, the summing DAC and the meaning of resolution and number of levels.

higher level

The full A-Level develops quantisation error and the flash and successive-approximation ADC architectures with quantitative code calculations.

Contents · 4 sections

Signal conversion

4 sections8 key takeaways6 formulas8 mistake warnings

Why convert, and sampling#

~4 min reading timeStandardWJEC/Eduqas A Level Electronics — Unit 4 Digital and Communication (data conversion)

The analogue-digital-analogue signal chain

Fig. 1The conversion sub-systems bridge the analogue world and digital processing: transducer, ADC, digital process, DAC, output transducer.

The quantities we sense and act on — temperature, sound, light, position — vary continuously and are naturally analogue, but the powerful, cheap, noise-immune processing of a microprocessor is digital. A modern system therefore sits between the two worlds: an input transducer produces an analogue signal, an analogue-to-digital converter (ADC) turns it into numbers, the processor manipulates those numbers, and a digital-to-analogue converter (DAC) turns the result back into an analogue signal to drive an output transducer. Conversion is the bridge between the analogue world and digital processing.

Digital representation brings real advantages that justify the extra converters. A number is immune to the noise that would corrupt a delicate analogue voltage — it can be stored, copied and transmitted perfectly, and regenerated along a long link. It can also be processed in ways that are impossible in the analogue domain: filtered, compressed, error-corrected and combined under program control. These benefits are why almost every audio, communication and control system now converts to digital as early as possible and back to analogue as late as possible.

To turn a continuous signal into numbers, the ADC samples it — measures its value at regular instants — and then quantises each sample to the nearest of a finite set of levels. Sampling chops the signal in time; quantising rounds it in amplitude. The sampling must be fast enough to capture the signal's changes: the sampling rate must be at least twice the highest frequency present (the Nyquist criterion, developed fully in the digital-communications chapter), or the reconstructed signal is distorted by aliasing.

Between the sample instants the ADC knows nothing, and each sample is rounded to a level, so a digitised signal is only an approximation to the original. The art of conversion is to make that approximation good enough — sampling fast enough in time and with enough levels in amplitude — without wasting speed, memory or cost on more precision than the application needs. This trade-off between fidelity and resource, made quantitatively, is exactly the kind of design judgement the A2 paper examines.

In the systems language of the course, the ADC and DAC are the interface sub-systems that let a digital process stage act on analogue inputs and outputs. The whole signal chain — input transducer, ADC, digital process, DAC, output transducer — is a clear input-process-output structure, and recognising where conversion sits in it, and why, is the foundation for everything that follows in this chapter.

Levels from n bits

\text{levels} = 2^n

An n-bit converter distinguishes 2^n amplitude levels.

Worked example

How many levels and how fine?

An audio signal contains frequencies up to $20\,\text{kHz}$ and is digitised by an $8$ -bit ADC with a $0$ to $5.12\,\text{V}$ range. State the minimum sampling rate, the number of levels and the smallest voltage step.

Sampling rate
By the Nyquist criterion the rate must be at least twice the highest frequency: $2 \times 20\,\text{kHz} = 40\,\text{kHz}$ .
Number of levels
$8$ bits give $2^8 = 256$ distinct levels.
Step size
The step is the range divided by the number of levels: $5.12/256 = 0.020\,\text{V} = 20\,\text{mV}$ .
$\text{step} = \dfrac{5.12\,\text{V}}{2^8} = 20\,\text{mV}$

Result: Sample at $\geq 40\,\text{kHz}$ ; $256$ levels give a $20\,\text{mV}$ step — fine enough for the $5.12\,\text{V}$ range.

Typical mistakes

Confusing sampling (in time) with quantising (in amplitude) — they are two separate approximations.
Assuming any sampling rate will do; it must be at least twice the highest signal frequency.

Active revision

Sketch the block diagram of a digital audio system from microphone to loudspeaker, naming the ADC and DAC, and state one advantage of processing the sound digitally.

Practise matching questions

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

The summing (binary-weighted) DAC#

~4 min reading timeStandardWJEC/Eduqas A Level Electronics — Unit 4 Digital and Communication (DAC)

Binary-weighted DAC

Fig. 2Each bit drives the virtual earth through a resistor scaled by its place value (

R, 2R, 4R, 8R

); the summing op-amp turns the total current into a proportional output.

A digital-to-analogue converter turns a binary number into a proportional analogue voltage, and the neatest way to build one uses the summing amplifier from the op-amp chapter. Each bit of the binary input is fed through its own resistor into the virtual earth of an inverting op-amp, and the resistors are scaled by the place value of their bit: the most significant bit uses the smallest resistor and so contributes the most current, and each less significant bit uses a resistor twice as large, contributing half as much.

Because the input resistors are in the ratio

R : 2R : 4R : 8R

for successive bits, the currents they inject are in the ratio

8 : 4 : 2 : 1

— exactly the binary place values. The virtual earth sums these currents, and the feedback resistor turns the total into an output voltage. The result is that the analogue output is directly proportional to the binary number applied to the switches, so counting up in binary produces a rising staircase of output voltage.

The output can be written as the full-scale voltage multiplied by the fraction that the input number represents of the maximum. For an

n

-bit converter the maximum count is

2^n - 1

, so an input of decimal value

D

gives an output

V_{out} = V_{FS} \times D/2^n

(or

D/(2^n)

per step). Each increase of one in the input number changes the output by one step — the DAC's resolution — and stepping the input through all its values sweeps the output across the full range in equal increments.

The binary-weighted DAC is simple to understand but has a practical weakness: for many bits the resistor values span a huge range (the ratio between the smallest and largest is

2^{n-1}

), and making the largest resistors precise enough is difficult. The R-2R ladder DAC solves this by using only two resistor values,

R

and

2R

, repeated in a ladder network that produces the same binary weighting. Knowing that the R-2R ladder achieves the same result with only two resistor values is a common evaluation point.

The DAC is the output interface of a digital system: it reconstructs an analogue signal from the stream of numbers a processor produces, so that the signal can drive a loudspeaker, a motor or a display. Following its output with a low-pass reconstruction filter smooths the staircase into a continuous waveform. Recognising the DAC as a weighted summing amplifier ties this chapter directly back to the op-amp work and shows how the building blocks of the course combine.

DAC output

V_{out} = V_{FS} \times \dfrac{D}{2^n}

Output proportional to the input number D for an n-bit converter.

Binary weighting

R : 2R : 4R : 8R \Rightarrow I \text{ in ratio } 8:4:2:1

Halving the resistor doubles the current, giving successive binary place values.

Worked example

Output codes of a 4-bit DAC

A 4-bit binary-weighted DAC gives $8.0\,\text{V}$ at full scale (input $1111$ is treated as the maximum, with $16$ steps). Find the step size and the output for $0001$ , $1000$ and $1010$ .

Step size
With $2^4 = 16$ steps over the range, one step is $8.0/16 = 0.50\,\text{V}$ (this is the output for $0001$ ).
Input 1000
$1000_2 = 8$ , so $V_{out} = 8 \times 0.50 = 4.0\,\text{V}$ — half of full scale, as expected for the MSB alone.
Input 1010
$1010_2 = 10$ , so $V_{out} = 10 \times 0.50 = 5.0\,\text{V}$ .
$V_{out} = 10 \times 0.50\,\text{V} = 5.0\,\text{V}$

Result: Step $0.50\,\text{V}$ ; outputs are $0.50\,\text{V}$ ( $0001$ ), $4.0\,\text{V}$ ( $1000$ ) and $5.0\,\text{V}$ ( $1010$ ) — proportional to the input number.

Typical mistakes

Getting the resistor weighting backwards — the most significant bit uses the smallest resistor (largest current).
Forgetting that the output is proportional to the input number, so it rises in equal steps as the count increases.

Active revision

A 4-bit binary-weighted DAC has a full-scale output of $8.0\,\text{V}$ (for input $1111$ ). Find the output for the input codes $0001$ , $1000$ and $1010$ , and state the size of one step.

Practise matching questions

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

Resolution and quantisation#

~4 min reading timeAdvancedWJEC/Eduqas A Level Electronics — Unit 4 Digital and Communication (resolution)

Quantisation staircase

Fig. 3The ideal converter follows the diagonal; the real converter's output is a staircase. The vertical gap between them is the quantisation error, up to half a step.

Resolution is the smallest change in analogue signal that a converter can distinguish — one step, or one least-significant bit. For a converter with an input range (full scale)

V_{FS}

and

n

bits, the number of levels is

2^n

and the step size is

V_{FS}/2^n

. Adding one bit doubles the number of levels and halves the step, so resolution improves rapidly with bit count: an 8-bit converter resolves to

1/256

of full scale, a 12-bit one to

1/4096

Because a continuous input must be rounded to the nearest available level, there is an unavoidable error between the true value and its digital representation. This quantisation error can be as large as half a step (

\pm\tfrac{1}{2}

LSB), and it appears as a kind of noise on the reconstructed signal. Increasing the number of bits reduces the step and hence the quantisation error, which is why high-fidelity audio uses 16 bits or more — the finer the steps, the smaller the rounding noise.

Plotting the digital output against the analogue input gives a staircase: the output holds constant across each band of input values a step wide, then jumps to the next level. The ideal, infinitely fine converter would follow the straight diagonal line; the real converter's staircase deviates from it by up to half a step at every point. The vertical gap between the staircase and the diagonal is the quantisation error, and seeing it drawn makes the meaning of resolution concrete.

There is a direct trade-off between resolution and cost, speed and data rate. More bits mean finer resolution but a more complex, expensive converter, and more bits per sample means more data to store or transmit. The designer chooses the smallest number of bits that keeps the quantisation error below what the application can tolerate — for a temperature display a few bits may suffice, while for professional audio many are needed. Justifying a bit count against a required resolution is a classic AO3 question.

To find the digital code for a given input, divide the input by the step size and round to the nearest whole number; to find the reconstructed voltage, multiply the code by the step. The difference between the original input and this reconstructed value is the quantisation error for that sample. Being fluent with these three calculations — step size, code, and error — and relating them to the number of bits, is the central quantitative skill of the conversion chapter.

Resolution

\text{step} = \dfrac{V_{FS}}{2^n}, \quad \text{levels} = 2^n

Step size is full scale divided by the number of levels.

Quantisation error

\text{max quantisation error} = \pm\tfrac{1}{2}\,\text{step}

Rounding to the nearest level can be wrong by up to half a step.

Resolution versus bit count

Fig. 4How resolution improves with bits for a

5.12\,\text{V}

full-scale range: each extra bit halves the step size.

Worked example

Code and quantisation error

An 8-bit ADC digitises the range $0$ to $5.12\,\text{V}$ . Find the step size, the code for an input of $3.60\,\text{V}$ , the reconstructed voltage and the maximum quantisation error.

Step size
$\text{step} = V_{FS}/2^n = 5.12/256 = 0.020\,\text{V} = 20\,\text{mV}$ .
Code
$\text{code} = \text{round}(3.60/0.020) = \text{round}(180) = 180$ , which is $10110100$ in binary.
Reconstructed voltage and error
Reconstructed $= 180 \times 0.020 = 3.60\,\text{V}$ ; the maximum quantisation error is $\pm\tfrac{1}{2}\,\text{step} = \pm 10\,\text{mV}$ .
$\text{error}_{max} = \pm\tfrac{1}{2}(20\,\text{mV}) = \pm 10\,\text{mV}$

Result: Step $20\,\text{mV}$ ; $3.60\,\text{V}$ gives code $180$ ( $10110100$ ), and the quantisation error is at most $\pm 10\,\text{mV}$ .

Typical mistakes

Confusing the number of levels ( $2^n$ ) with the maximum code ( $2^n - 1$ ).
Quoting the maximum quantisation error as one step rather than half a step.

Active revision

An 8-bit ADC has a $0$ to $5.12\,\text{V}$ range. Find the step size, the code produced by an input of $3.60\,\text{V}$ , and the maximum quantisation error.

Practise matching questions

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

ADC architectures#

~4 min reading timeAdvancedWJEC/Eduqas A Level Electronics — Unit 4 Digital and Communication (ADC)

Successive-approximation ADC

Fig. 5The register guesses the code one bit at a time; its internal DAC output is compared with the input, and each bit is kept or cleared before moving to the next.

There are several ways to build an ADC, differing in how they search for the code that matches the input. The flash (parallel) converter is the fastest: it compares the input simultaneously against every possible level using a bank of comparators — one per level — and a priority encoder turns the pattern of comparator outputs directly into the binary code in a single step. An

n

-bit flash ADC needs

2^n - 1

comparators, so it is very fast but grows expensive and power-hungry as the bit count rises.

The successive-approximation ADC is the workhorse compromise. It contains an internal DAC, a comparator and a control register that guesses the code one bit at a time, starting with the most significant. It sets the top bit, uses the DAC to compare that guess against the input, and keeps the bit if the guess is still below the input or clears it if the guess overshoots; it then moves to the next bit and repeats. After

n

such steps the register holds the correct code.

This binary-search strategy is efficient: an

n

-bit conversion takes only

n

comparisons, not

2^n

, so a 10-bit converter needs just ten steps. The successive-approximation ADC therefore offers a good balance of speed, resolution and cost, and is the type found in most microcontrollers. Being able to trace the bit-by-bit search — set a bit, compare, keep or clear, move on — for a given input is a favourite exam task because it shows genuine understanding of the mechanism.

The two architectures illustrate a general design trade-off between speed and cost. The flash converter buys the highest speed with a large amount of hardware; the successive-approximation converter accepts a slower, multi-step conversion in exchange for far less hardware. A third family, the ramp or dual-slope converter, is slower still but very simple and accurate, and is used where speed does not matter, such as a digital voltmeter. Matching the converter type to the demands of the application is the design judgement the examiner rewards.

Whatever the architecture, every ADC performs the same function — sample, quantise, encode — and is limited by the same resolution and quantisation ideas of the previous section. The choice of architecture affects how fast and how cheaply the conversion is done, not what the numbers mean. Recognising that the flash and successive-approximation converters are two routes to the same digital code, chosen by weighing speed against cost, ties the conversion chapter together and prepares the ground for the communication systems that transmit those codes.

Converter cost and speed

\text{flash: } 2^n - 1 \text{ comparators}, \quad \text{SAR: } n \text{ steps}

Flash is fastest but hardware-heavy; successive approximation needs only n comparisons.

Worked example

Tracing a successive-approximation conversion

A 4-bit successive-approximation ADC has bit weights $4\,\text{V}, 2\,\text{V}, 1\,\text{V}, 0.5\,\text{V}$ (MSB to LSB). Convert an input of $5.5\,\text{V}$ .

Bit 3 (4 V)
Try $1000 = 4\,\text{V}$ . Since $4 \leq 5.5$ , keep the bit: code so far $1000$ .
Bit 2 (2 V)
Try $1100 = 6\,\text{V}$ . Since $6 > 5.5$ , clear the bit: code back to $1000$ .
Bit 1 (1 V)
Try $1010 = 5\,\text{V}$ . Since $5 \leq 5.5$ , keep the bit: code $1010$ .
Bit 0 (0.5 V)
Try $1011 = 5.5\,\text{V}$ . Since $5.5 \leq 5.5$ , keep the bit: final code $1011$ .
$1011_2 = 4 + 1 + 0.5 = 5.5\,\text{V}$

Result: The conversion completes in four steps with the code $1011$ , representing exactly $5.5\,\text{V}$ .

Typical mistakes

Thinking a successive-approximation ADC tries every code — it does a binary search, taking only n steps for n bits.
Forgetting that a flash ADC needs $2^n - 1$ comparators, so the hardware doubles with each extra bit.

Active revision

A 4-bit successive-approximation ADC has a reference such that the bit weights are $4\,\text{V}, 2\,\text{V}, 1\,\text{V}, 0.5\,\text{V}$ . Trace the conversion of an input of $5.5\,\text{V}$ and give the final code.

Practise matching questions

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

Full version via the depth control — same place, same anchors

Plan a review

References & sources

Sources

WJEC / Eduqas

WJEC/Eduqas GCE Electronics specification

Signal conversion

4 sections~15 min reading time3 competencies

Signal conversion

Key points

How many levels and how fine?

Key points

Output codes of a 4-bit DAC

Key points

Code and quantisation error

Key points

Tracing a successive-approximation conversion

Sources

Signal conversion

Key points

How many levels and how fine?

Key points

Output codes of a 4-bit DAC

Key points

Code and quantisation error

Key points

Tracing a successive-approximation conversion

Sources